Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate.
As millions and millions of devices and circuits are squeezed on a semiconductor chip, the wiring density and the number of metal levels are both increased generation after generation. In order to provide low RC for high signal speed, low k dielectric materials having a dielectric constant of less than silicon dioxide as well as copper-containing lines are becoming a necessity. The quality of thin metal wirings and studs formed by a conventional damascene process is extremely important to ensure yield and reliability.
The major problem encountered in this area today is poor mechanical integrity of deep submicron metal studs embedded in low k dielectric materials, which can cause unsatisfied thermal cycling and stress migration resistance in interconnect structures. This problem becomes more severe when either new metallization approaches or porous low k dielectric materials are used.
To solve this weak mechanical strength issue while employing copper damascene and low k dielectric materials in an interconnect structure, a so called “via punch-through” technique has been adopted by the semiconductor industry. The via punch-through provides a via gouging feature (or anchoring area) within the interconnect structure. Via gouging features are reported to achieve a reasonable contact resistance as well as an increased mechanical strength of the contact stud. See, for example, in M.-Si Liang “Challenges in Cu/Low k Integration”, IEEE Int. Electron Devices Meeting, 313 (2004), D. Edelstein et al. “Comprehensive Reliability Evaluation of a 90 nm CMOS Technology with Cu/PECVD Low k BEOL”, IEEE Int. Reliability Physics Symp., 316 (2004), and U.S. Pat. Nos. 4,184,909 to Chang et al., 5,933,753 to Simon et al., 5,985,762 to Geffken et al., 6,429,519 to Uzoh and 6,784,105 to Yang et al.
However, the argon sputtering technique that is used to create via gouging in the prior art not only removes the deposited liner material, e.g., TaN, from the trench (i.e., line opening) bottom, but also damages the low k dielectric material; the damage is in the form of increased surface roughness which forms at the bottom of the trench formed into the low k dielectric material. Because of the requirement of creating the gouging feature, the final interconnect structure not only has poor liner coverage at the trench bottom, but severe damage has been introduced into the low k dielectric material from the Ar sputtering process. This becomes a major yield detractor and a reliability concern for advanced chip manufacturing.
The detailed processing steps of the existing prior art approach for via gouging are illustrated in FIGS. 1A-1E and are described herein below. Reference is first made to FIG. 1A which illustrates a prior art structure that is formed after dual damascene patterning of an upper interconnect level 108 which is located atop a lower interconnect level 100. The lower interconnect level 100 includes a first low k dielectric material 102 which includes a metallic, Cu, feature 104 therein. The lower interconnect level 100 is separated in part from the upper interconnect level 108 by a capping layer 106. The upper interconnect level 108 includes a second low k dielectric material 110 that includes both line 112 and via 114 openings located therein. A surface of the metallic feature 104 of the lower interconnect level 100 that is beneath the via opening 114 is exposed as is shown in FIG. 1A.
FIG. 1B shows the prior art structure of FIG. 1A after forming a diffusion barrier, e.g., TaN, 116 over all of the exposed surfaces. Argon sputtering, such as is shown in FIG. 1C, is then performed to clean the bottom horizontal surface within the via opening 114 and form a gouging feature (i.e., anchoring area) 118 into the metallic feature 104 of the lower interconnect level 100. The gouging feature 118 is employed to enhance the interconnect strength between the various interconnect levels shown. During the Ar sputtering process, the diffusion barrier 116 is removed from the bottom of each of the line openings 112, and dielectric damages 120 (which are indicated by circles in the second low k dielectric material 110) are formed at the bottom of each of the line openings 112. The dielectric damages 120 formed during the sputtering process are due to the inherent aggressive nature of prior art sputtering processes.
FIG. 1D shows the prior art structure of FIG. 1C after forming a metal liner layer, e.g., Ta, Ru, Ir, Rh or Pt, 122 on the exposed surfaces thereof. FIG. 1E illustrates the prior art structure after filling the line and via openings (112 and 114, respectively) with a conductive metal, e.g., Cu, 124 and planarization. As shown in FIG. 1E, the prior art structure has poor diffusion barrier 116 coverage (designated by reference numeral 126) at the bottom of the metallic filled lines and a feature-bottom roughness which is a result of the damages 120 formed into the second low k dielectric material 110. Both of these characteristics reduce the quality of the diffusion barrier 116 and degrade the overall wiring reliability. Moreover, both of the aforementioned characteristics result in the structure exhibiting a high-level of metal-to-metal leakage.
Porous ultra-low k dielectric materials (having a dielectric constant of about 2.8 or less) have been developed and have been used in interconnect structures as one of the interlevel dielectrics. As compared to dense (i.e., non-porous) low k dielectrics, the damage impact of argon sputtering is much higher on most ultra-low k dielectric materials tested, which makes integration of the current metallization approach (See FIGS. 1A-1E, for example) with ultra-low k dielectric materials nearly impossible. As a result, all of the current ultra-low k hardware has failed during barrier integrity testing.
In view of the above drawbacks with prior art interconnect structures, and particularly in those including a porous ultra-low k dielectric as one of the interlevel dielectric materials, there is a continued need for developing a new and improved integration scheme that avoids the problem mentioned above with prior art interconnect integration schemes.
U.S. Patent Application Publication No. 2007/0205482 A1 to Yang et al. (hereinafter the '482 publication) provides one possible solution to the above-mentioned problem. Specifically, the '482 publication provides a method of fabricating a semiconductor interconnect structure in which the damages mentioned above with respect to prior art processing have been eliminated. The method of the '482 publication includes first providing an initial interconnect structure that includes a lower interconnect level comprising a first dielectric material having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric material having at least one via opening that exposes a portion of the at least one conductive feature located atop the lower interconnect level, said lower and upper interconnect levels are separated in part by a dielectric capping layer, and a patterned hard mask on a surface of the upper interconnect level. A first barrier layer is then formed on all exposed surfaces of the initial interconnect structure including atop the patterned hard mask, on the sidewalls of the second dielectric material within the at least one opening and on the at least one conductive feature formed in the first dielectric material. A punch-through gouging feature is then formed into the at least one conductive feature that is located at the bottom of the via opening by Ar sputtering; the Ar sputtering process removes the first diffusion barrier layer from all horizontal surfaces of the structure, while leaving a portion of the first barrier layer along the sidewalls of the at least one opening formed into the second dielectric layer. A metallic interfacial layer is thereafter optionally formed atop the gouging feature.
Next, at least one line opening is formed in the second dielectric material that extends above the at least one via opening. Any etching residues are removed from the at least one line opening and from the at least one via opening utilizing a surface cleaning process such as, for example, wet chemical etching and/or a slight Ar bombardment. Next, a second continuous diffusion barrier layer is formed at least within the at least one line opening, and then an adhesion/plating seed layer is formed within both the at least one line opening and the at least one via opening. The at least one line opening and at least one via opening are then filled with a conductive material.
The resultant interconnect structure formed by this process includes the presence of two different barrier materials within the conductively filled opening. See, for example, FIGS. 12A-12B of the '482 publication in which reference numeral 30 represents the first barrier material and reference numeral 46 represents the second barrier material). Also, the prior art process includes the use of a simultaneous metal/dielectric etching process during the formation of the at least one line opening. Currently, the processing scheme of the '482 publication is not a preferred process for manufacturing interconnect structures.
As such, there is still a demand for providing an improved interconnect integration scheme that avoids the problems mentioned above with prior art interconnect integration schemes.